1. Field of the Invention
The present invention relates to non-volatile memory arrays. In particular it relates to push-pull non-volatile memory cells for use in flash based Field Programmable Gate Arrays.
2. The Prior Art
NOR flash memories are known in the art. Over-erase is an issue very commonly encountered in traditional NOR flash memory schemes. In a NOR flash memory array, each memory cell is a single n-channel non-volatile transistor with its control gate coupled to a row line that is also coupled to all of the other control gates in the same row, its drain coupled to a bit line which is coupled to the drain of every other non-volatile transistor in the same column, and a source line which can be either a second row line or a second column line as a matter of design choice.
Over-erase typically occurs during a bulk erase operation of a memory block. This is typically done by driving the control gates of all the non-volatile transistors in the array to a large negative voltage and all of the source and drain nodes as well as the background material (typically a high voltage P-well for n-channel non-volatile transistors) to a much higher voltage that is typically ground. Alternatively the large negative voltage is split between a lesser negative voltage and a positive voltage. This causes electrons to tunnel off of the floating gate reducing the threshold voltage of the transistors to a negative threshold voltage. A negative threshold voltage means that the transistor will conduct current (also known as being “on”) with 0V of control gate node voltage bias relative to the source node.
There is a distribution of the negative threshold voltages of the memory cells due to random manufacturing variations. Subsequent to the erase operation, some of the cells must be programmed to place them in the off condition. Hot carrier injection (or HCI) is commonly used for programming in the industry. Typically the polysilicon control gate and the drain of the memory device must be taken to a high positive voltage and significant current is then passed through the transistor channel diffusion to generate hot (or high energy) electrons that have enough energy to pass through the gate oxide to the floating gate and therefore place a negative charge on the floating gate to raise the threshold voltage, typically to a positive value. A positive threshold voltage means that the transistor will not conduct current (also known as being “off”) with 0V of gate node voltage bias relative to the source node. To do this, all other row lines on the column must turn their memory cells off or the other memory cells on the column will pass current as well and prevent the intended cell from programming by depriving it of available programming current. If the Erase Vt on one memory cell is too negative due to over-erase, then the over-erased memory cell will source enough current to inhibit programming other cells on the column even if its row line is properly driven negative. The same is true for the read condition where an over-erased memory cell can supply enough current to the column sense amplifier so that a properly programmed memory cell (i.e., the transistor is off and should source no read current) will appear to be erased (i.e., producing read current) due to the current of the over-erased cell, resulting in a reading error. It is therefore important that the erase distribution be controlled to prevent erased cells from being having too negative a threshold voltage.
In order to overcome this issue, a complicated smart erase scheme is typically implemented for the NOR erase. This involves erasing the array and then measuring the Vt of each cell (inferred by measuring the read current against a precisely known reference current) and then doing a “soft program” of the over-erased cells. This soft program is used to increase the Vt just enough to alleviate the over-erased condition while still leaving the threshold voltage sufficiently negative that each memory cell is still in the erased state. This is undesirable because it requires a substantial amount of complicated analog and control circuitry to implement.
Alternatively, a discrete access transistor is used in some NOR flash memory arrays. The access transistor can be used to block current through the non-volatile n-channel transistor to eliminate unwanted currents during programming or reading due to an over-erase condition. This is highly undesirable because adding a second transistor typically doubles the size of the memory cell, effectively halving the attainable memory density at any given process node.
A technique known as split gate can be used to provide an access transistor in a fraction of the area. A first row line is run in polysilicon at the normal width to produce an access transistor of minimum channel length. Then a second row line of control gate polysilicon above (also at the width for minimum transistor channel length with non-volatile transistor charge storage material aligned to and underneath it) is overlaid somewhat offset relative to the first row line, creating a memory transistor immediately adjacent to the access transistor. This effectively creates two transistors at each memory cell location: an n-channel volatile transistor under the first row line and a n-channel non-volatile transistor in series with it under the part of the second row line that is not over the first row line. This is undesirable because it complicates the semiconductor processing to produce the special split gate devices and increases the area of the memory cell (though much less than adding a discrete access transistor without any special processing).
Field Programmable Gate Array (FPGA) integrated circuit devices are known in the art. An FPGA comprises any number of initially uncommitted logic modules arranged in an array along with an appropriate amount of initially uncommitted routing resources. Logic modules are circuits which can be configured to perform a variety of logic functions like, for example, AND-gates, OR-gates, NAND-gates, NOR-gates, XOR-gates, XNOR-gates, inverters, multiplexers, adders, latches, and flip/flops. Routing resources can include a mix of components such as wires, switches, multiplexers, and buffers. Logic modules, routing resources, and other features like, for example, I/O buffers and memory blocks, are the programmable elements of the FPGA.
The programmable elements have associated control elements (sometimes known as programming bits or configuration bits) which determine their functionality. The control elements may be thought of as binary bits having values such as on/off, conductive/non-conductive, true/false, or logic-1/logic-0 depending on the context. The control elements vary according to the technology employed and their mode of data storage may be either volatile or non-volatile. Volatile control elements, such as SRAM bits, lose their programming data when the PLD power supply is disconnected, disabled or turned off. Non-volatile control elements, such as antifuses and floating gate transistors, do not lose their programming data when the PLD power supply is removed. Some control elements, such as antifuses, can be programmed only one time and cannot be erased. Other control elements, such as SRAM bits and floating gate transistors, can have their programming data erased and may be reprogrammed many times. The detailed circuit implementation of the functional blocks and routing resources can vary greatly and is appropriate for the type of control element used.
Non-volatile push-pull FPGA control elements are known in the art. Typically these memory cells employ a series arrangement of a pull up transistor and a pull down transistor in a series arrangement where the common node produces either a logic-1 or logic-0 signal during normal operation of the FPGA (i.e., when the FPGA is implementing a user logic function instead of being in a control mode performing erase, program, or read operations on the contents of the FPGA control elements) and have fairly elaborate programming schemes.
Two prior art non-volatile push-pull FPGA cells are disclosed in U.S. Pat. No. 6,144,580 to Murray in FIG. 1 and FIG. 2. Each cell has a non-volatile p-channel pull-up transistor and a non-volatile n-channel pull-down transistor. The cell in FIG. 1 has a single row line while the cell in FIG. 2 has two row lines. One disadvantage to this approach is the complicated programming scheme needed to operate the cell in different modes as illustrated in FIG. 3 through FIG. 6 of Murray.
Another non-volatile push-pull FPGA cell is disclosed in U.S. Pat. No. 5,587,603 to Kowshik. FIG. 1 shows a cell with a non-volatile p-channel pull-up transistor and a non-volatile n-channel pull-down transistor with the charge storage gates of the non-volatile transistors being a single common floating gate shared by both transistors. A somewhat elaborate programming scheme involving an additional select transistor and an EEPROM style erase node is illustrated in Kowshik FIG. 5.
Some prior art non-volatile push-pull FPGA cells combine a mixture of volatile and non-volatile transistors. Several such cells using different non-volatile technologies are disclosed in U.S. Pat. No. 7,245,535 to McCollum, et al, (“McCollum”) in FIG. 1B through FIG. 1D. These cells combine a p-channel volatile pull-up transistor in a series arrangement with an n-channel non-volatile pull-down transistor, each cell employing a different non-volatile technology. A complimentary version of the cells with a p-channel non-volatile pull-up transistor in a series arrangement with an n-channel volatile pull-down transistor is also disclosed in FIG. 2B through FIG. 2D of McCollum.
Although these cells are shown in the McCollum figures with the p-channel volatile pull-up transistor sources coupled to Vcc and the n-channel non-volatile pull-down transistor sources coupled to ground, the discussion of the programming and erase operations indicates that the connections to VCC and ground are control lines driven to VCC and ground during FPGA normal operation and not hard connections to power supplies. While McCollum does not describe the programming and erase operations in detail, the tables in the middle of column 3 and at the top of column 5 hint at the degree of manipulation of the various device terminals required by the various cells in the first and second groups of cells respectively.
Control schemes for this style of memory cell are disclosed in U.S. Pat. No. 7,301,821 to Greene, et al, (“Greene”). The various schemes disclosed in Greene show that a great deal of manipulation of the gate, source and bulk (or P-well) terminals of the non-volatile transistor is done, requiring a significant amount of programming circuitry.